Introduction
We describe herein the manufacturability and performance of graphene-based spin and spin-polaron interconnects as a function of interconnect line width (W) and length (L), at or above room temperature. This effort reflects a combination of surface chemistry and growth studies with advanced patterning and charge transport measurements and spin transport and polarization studies. The objectives are threefold:
1) We demonstrate of the formation of graphene/dielectric heterostructures by manufacturable methods, including molecular beam epitaxy (MBE), atomic layer deposition (ALD), and plasma-enhanced chemical vapor deposition (PECVD). We have demonstrated the fabrication of such heterostructures previously, including graphene/BN formation [1], and graphene/Co3O4 formation [2].
2) We demonstrate the patterning of such structures for interconnect applications, with systematically varied W and L, using advanced lithographic methods.
3) We illustrate the measurement of charge and spin transport and related magnetic behaviors as function of interconnect W and L, for both diffusive spin transport and magnetic polaron spin transport (FIG. 1). Importantly, these measurements focus on performance at or above 300 K, rather than at cryogenic temperatures.
“Interconnects” or interconnections are the lines of conductive material printed or deposited to provide for electrical connection between electrically isolated or insulated devices or units that, once connected, form a “printed circuit.” Conventional SiCMOS based printed circuits have adopted copper interconnect technology. The precipitous increase in Cu interconnect resistivity with decreasing linewidth [3] poses a fundamental obstacle to continued complementary metal oxide semiconductor (CMOS) technology scaling. Recent findings, however, concerning long spin diffusion lengths at 4.2 K (˜4-100 μm) in graphene [4-6] support a beyond-Cu/CMOS interconnect architecture based on the transmission of spin, rather than charge.
“Conventional” graphene-based spintronics involves the injection and diffusive transport of discrete spin-polarized carriers [6]. Such devices are, as with conventional interconnects, impacted by sidewall scattering of discrete carriers [7]. While the magnetoresistance, being a ratio of conductances, might scale to smaller linewidths and unpolarized conductances, and exhibit lower energy usage characteristics [8] recent modeling suggests that such diffusive spin transport interconnects would display enhanced resistance at smaller W [7].
Spin polaron transport, as shown schematically in FIG. 1, involves the coherent spin polarization of graphene charge carriers due to exchange interactions with localized substrate spins (e.g., Co3O4) as in FIG. 1a. This results in formation of a “spin polaron” state stabilized relative to the system ground state by these exchange interactions (FIG. 1b). Such interactions occur in Mn+2-doped CdTe quantum wells [9], and have recently been indicated in graphene/Co3O4/Co(0001) heterostructures, at and above 300 K [10] (FIG. 1c). Since such spin polarons are manifested due to interfacial exchange interactions, they should be relatively unaffected by sidewall scattering. Indeed, preliminary calculations indicate the maintenance of such spin polarons to W˜50 nm, and possibly to much smaller dimensions. This is in contrast to Cu interconnects, where significant increases in resistance are observed at or below W˜80 nm [3].
We compare herein the different responses of diffusive vs. magnetic polaron spin transport to sidewall scattering at small W and large L. Additionally, we explore the potential for novel, hybrid structures combining traditional interconnect and switching functions, with the potential for truly innovative spin-based architectures that differ qualitatively from Cu/Si/CMOS. The potential of graphene-based spin devices for high speed/low power device applications has recently been modeled [8]. The ability of graphene-based structures to combine both interconnect/device/memory capabilities into new, disruptive hybrid functionalities provides an additional and powerful motivation for the proposed research.
Related Art
The references cited at the end of this specification are identified largely for the purposes of illustrating the problems and the structures of the prior art. It is only in the context of such prior art that the interconnect advance of this case can be properly understood. Nonetheless, the disclosures of these references may be helpful in understanding how to properly form and use the inventive subject matter disclosed herein, and to that extent, they are incorporated herein-by-reference.